1. Field of the Invention
The invention relates to a method for fabricating a semiconductor device, and in more particularly relates to a method for fabricating an alignment mark or an overlay mark of a semiconductor device.
2. Description of the Related Art
In recent years, semiconductor device fabricating technology has continually sought new ways to achieve high device performance, lower costs, and high device densities. For example, in the case of a dynamic random access memory (DRAM), high device densities are used for forming high aspect ratio trench capacitor structures during DRAM fabrication. FIG. 1a shows a schematic top view of a substrate of a conventional semiconductor device 100. The substrate of the conventional semiconductor device 100 comprises a device region 102 and a testkey region 104. The device region 102 is a region for forming patterns comprising trench capacitors, periphery circuits or dummys. The testkey region 104 is a region for forming patterns comprising alignment marks, overlay marks or critical dimension (CD) testkeys. As shown in FIGS. 1b to 1d, the conventional alignment mark or overlay mark testkeys may have various shapes.
During the fabricating processes of the conventional DRAM, a single side buried strap (SSBS) can be used to electrically connect a trench capacitor plate and a source of a subsequent transistor. FIG. 1e is a cross section taken along line A-A′ of FIG. 1a showing topography of the device region 102 and testkey region 104 after forming the conventional single side buried strap (SSBS) 124. After performing the conventional trench capacitor fabricating process, a first trench capacitor 120a and SSBS 124 are formed in a first trench 110 on the device region 102 while a second trench capacitor 120b and another SSBS 124 are formed in a second trench 112 on the testkey region 104. The conventional DRAM fabricating process comprising SSBS 124 on device region 102, however, causes an asymmetric profile to a central axis 170 on testkey region 104 as shown in FIG. 1e. The patterns on the testkey region 104, for example, alignment marks or overlay marks, are usually used to control relative positioning of the testkey region 104 between laminated layers. However, alignment marks with asymmetric profiles causes optical signal judgment problems for inspection machines used in the photolithography processes. The optical signal judgment problems result from a misalignment or overlay error problem during the photolithography processes. As a result, the problems reduce yield and device reliability of the conventional DRAM fabricating processes.
Thus, a novel and reliable method for fabricating alignment marks or overlay marks of a semiconductor device without an asymmetric profile is needed.